Switched power supplies have numerous applications in electronic devices, lighting, and motor drives, and several basic types are well known to those skilled in the art. As the art of switched power supplies has developed, the various system components were first implemented as analog circuits.
FIG. 1 illustrates in simplified form, the general architecture of a single phase analog switched power supply 100. For consistency of description, the topology shown is that of the synchronous buck converter, but again, it is to be understood that the context is for illustrative purposes only.
The exemplary device 100 includes a high-side switch 105, a low-side switch 110 connected to the high-side switch at a switch node 115, an output inductor 120 connected to the switch node 115, and an output capacitor 125 connected to the output inductor 120. High and low-side switches 105 and 110 may be power MOSFETS, IGBTS, or other bipolar transistors or other suitable devices which can be switched between a highly conductive state and a substantially non-conductive state.
The DC power is provided to a DC bus 150 from an AC source through a suitable rectification circuit (not shown) of any conventional type well known to those skilled in the art.
In operation, gate drive signals for the high-side and low-side switches 105 and 110 are provided at 140 and 145 respectively by a control circuit 130 to produce a desired output voltage across a load 135, which might, for example, be an electronic device such as a computer or an electric motor. For this purpose, control circuit 130 includes logic circuits which control the on and off times (duty cycle) of the switches.
Duty cycle control is customarily provided by pulse width modulation derived from a repetitive triangular waveform which is compared to an error signal to generate PWM duty cycle pulses which are provided to a suitable gate drive circuit.
To meet the load current demand while providing adequately regulated voltage, a suitable feedback regulation loop 155 is provided by which signals representing relevant operating parameters such a load current or output voltage are transferred to control circuit 130. Control circuit 130 utilizes these signals to provide compensation, filtering, or other signal processing, and to control the switching times of switches 105 and 110.
The illustrated configuration and its manner of operation are well known to those skilled in the art, and further description will be omitted in the interest of brevity.
Where the current demand of the load exceeds what can conveniently be provided by the circuit of FIG. 1, or for powering large industrial motors, multiple circuits can be combined as illustrated at 200 in FIG. 2. Here, multiple output phases 205a, 205b, . . . , 205n feed load 135 through separate inductors 215a, etc. and output capacitor 125. When the load is a multi-phase motor, each phase 205a, 205b, . . . 205n one of the phase windings of the motor through a separate LC circuit.
Control of the power supply is provided by a suitable multi-phase control circuit 210, and a feedback circuit (not shown) of any suitable design, as will be understood by those skilled in the art.
Although switched power supplies implemented using analog technology are in widespread use, numerous advantages of digital implementation over analog for test and measurement, machine control, motor control, and communication are now recognized. Among these are intelligent fault resolution, accurate timing, unit-to-unit repeatability, lack of component drift over time and temperature, firmware design control, and accuracy of implementing complex functions. As these became well known, the application of digital techniques to power supply design to began to receive serious consideration.
FIG. 3 illustrates the architecture of a switched PWM power supply (again in the exemplary context of a synchronous buck converter) implemented using digital technology. Here, the switching is performed by high and low side switches 302 and 304 (shown as MOSFETS) connected between a positive DC bus 308 and ground 310 or, depending on the application, positive and negative DC busses. A common node 306 between the switches is connected through an inductor 312 to an output capacitor 314 to drive a load 316.
A gate drive unit 318 which includes a dead time control circuit 364 and gate drivers 366 and 368, as well as any other conventional or desired circuitry, receives PWM duty cycle control signals at terminal 320 from the PWM logic generally denoted at 322, and described more fully below.
In a digitally implemented switched power supply, the control loop may typically include one or more sensors (not shown), outputs of which are provided on a signaling path 354, and are digitized in an A/D converter 352 of any conventional or desired design. The output of A/D converter 352 is provided over a signal bus 356 to a digital conditioning unit 358. This may be implemented as a programmed microprocessor, a digital signal processor, an ASIC, or in any other suitable or desired manner to provide digital filtering, and compensation according any suitable or desired compensation algorithm customarily employed in analog or digital switching power supply control loops including, but not limited to non-linear control functions or lookup tables. This creates an error “signal” in the form of a numeric representation of the compensated feedback signal on a signal bus 360.
The numerical error information on signal bus 360 is applied directly to digital logic unit 322 which generates the PWM gate drive signals for switches 302 and 304. Logic unit 322 includes a down counter 362 and a master clock 324 connected to drive counter 362, and to set a latching circuit 326 through a divider circuit 328. A reset signal for latch 326 is provided by the underflow or “borrow” output of counter 362. The latch reset output, in turn, provides a cycle start signal to counter 362 to load the error signal on bus 360. The output of latch circuit 326 is used to generate the PWM duty cycle pulses which are provided to the gate drive circuit 318 described above.
As illustrated, 8 bit logic is employed. Master clock 324 runs at 256 Mhz whereby down counter 362 is clocked at 256 Mhz. Divider 328 provides a divide by 256 function whereby a 1 Mhz signal is provided to set PWM latch 326.
Adoption of digital control techniques for motor drive, lighting, and other low frequency switching applications has progressed well, but adoption of digital control for high frequency switching power supply design has been slow due to high cost, despite the potential benefits.
Also, an inherent limitation with digital implementation exists when power supplies are operated simultaneously at high switching frequencies to accommodate rapid load transients, and with high accuracy to provide good output voltage stability. This problem is caused by the fact that any increments in pulse width for a true digital PWM can be no shorter than the main clock frequency. Consider, for example, a PWM system driven by a 100 Mhz clock, for which the minimum pulse width change is 10 ns. For a 1 Mhz PWM frequency, the switching interval pulse width is on the order of 100 ns, so individual duty cycle step changes (10 ns) can only be 10% of the switching interval. In most instances, this simply can not yield the required accuracy. Even if the PWM frequency can be reduced to 100 Khz, the step change is only 1%, which is inadequate for many power supplies.
Thus a need clearly exists for digital power supply implementation which provides the benefits of digital technology without the above described limitation.